82P33741 Datasheet, PDF (6/12 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 SHORT FORM DATA SHEET
Table 1: Pin Description (Continued)
Pin No.
G10
F10
E11
E10
E12
C12
L8
K5
M5
M6
M1
M2
A1
A2
A3
A4
C4
D12
D11
A8
B8
A6
B6
C9, A9, D8
A12
B12
A10
B10
Name
IN9
IN10
IN11
IN12
FRSYNC
_8K_1PPS
MFRSYNC
_2K_1PPS
OUT1
OUT2
OUT3_POS
OUT3_NEG
OUT4_POS
OUT4_NEG
OUT5_POS
OUT5_NEG
OUT6_POS
OUT6_NEG
OUT7
OUT8
OUT9
OUT10_POS
OUT10_NEG
OUT11_POS
OUT11_NEG
CAP1, CAP2,
CAP3
XTAL1_IN
XTAL1_OUT
XTAL2_IN
XTAL2_OUT
I/O
I
pull-down
I
pull-down
I
pull-down
I
pull-down
O
O
O
Type
Description
CMOS
CMOS
CMOS
CMOS
IN9: Input Clock 9
This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
IN10: Input Clock 10
This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
IN11: Input Clock 11
This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
IN12: Input Clock 12
This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
Output Frame Synchronization Signal
CMOS
CMOS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
An 8 kHz signal or a 1PPS sync signal is output on this pin.
MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output
A 2 kHz signal or a 1PPS sync signal is output on this pin.
Output Clock
CMOS ^{OUT1 ~ OUT2: Output Clock 1 ~ 2}
O
PECL/LVDS
OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3
The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4
The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5
The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
The LVDS output has internal 100 ohm termination.
O
CMOS OUT7: Output Clock 7
O
CMOS OUT8: Output Clock 8
O
CMOS OUT9: Output Clock 9
O
PECL ^{OUT10_POS / OUT10_NEG: Positive / Negative Output Clock 10}
O
PECL ^{OUT11_POS / OUT11_NEG: Positive / Negative Output Clock 11}
Miscellaneous
CAP1, CAP2 and CAP3: Analog Power Filter Capacitor connection 1 to 3. These capacitors
are be part of the power filtering.
Crystal oscillator 1 input.
I
Analog Determines first of two frequency families (Sonet/SDH, Ethernet or Ethernet*66/64) available
for APLL3. Connect to ground if XTAL1 is not used.
O
Analog
Crystal oscillator 1 output.
Leave open if XTAL1 is not used.
Crystal oscillator 2 input.
I
Analog Determines first of two frequency families (chosen from Sonet/SDH, Ethernet or Ethernet*66/
64) available for APLL3. Connect to ground if XTAL2 is not used
O
Analog
Crystal oscillator 2 output.
Leave open if XTAL2 is not used.
PORT SYNCHRONIZER FOR IEEE 1588 AND
6
10G/40G SYNCHRONOUS ETHERNET
REVISION 1 09/23/14