82P33741 Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – Differential reference inputs

82P33741 SHORT FORM DATA SHEET
1
PIN DESCRIPTION
Table 1: Pin Description
Pin No.
E1
A11
K6
H1
J1
J2
M12
M11
L12
L11
K12
K11
J12
J11
G12
G11
F12
F11
J10
H10
Name
OSCI
SONET/SDH/
LOS3
RSTB
XO_FREQ0/
LOS0
XO_FREQ1/
LOS1
XO_FREQ2/
LOS2
IN1_POS
IN1_NEG
IN2_POS
IN2_NEG
IN3_POS
IN3_NEG
IN4_POS
IN4_NEG
IN5_POS
IN5_NEG
IN6_POS
IN6_NEG
IN7
IN8
I/O
Type
Description
Global Control Signal
OSCI: Crystal Oscillator System Clock
I
CMOS A clock provided by a crystal oscillator is input on this pin. It is the system clock for the
device. The oscillator frequency is selected via pins XO_FREQ0 ~ XO_FREQ3.
I
pull-down
CMOS
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
LOS3- This pin is used to disqualify input clocks. See input clocks section for more details.
I
pull-up
CMOS
RSTB: Reset
A low pulse of at least 50 µs on this pin resets the device. If loading from an EEPROM, the
maximum time from RSTB de-assert to have stable clocks is 100 ms. If not loading from an
EEPROM, the maximum time from RSTB de-assert to have stable clocks is 5 ms.
I
pull-down
CMOS
XO_FREQ0 ~ XO_FREQ2: These pins set the oscillator frequency.
XO_FREQ[2:0] Oscillator Frequency (MHz)
000
10.000
001
12.800
010
13.000
011
19.440
100
20.000
101
24.576
110
25.000
111
30.720
LOS0 ~ LOS2 - These pins are used to disqualify input clocks. See input clocks section for
more details.
Input Clock and Frame Synchronization Input Signal
IN1_POS / IN1_NEG: Positive / Negative Input Clock 1
I
PECL/LVDS This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
IN2_POS / IN2_NEG: Positive / Negative Input Clock 2
I
PECL/LVDS This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
IN3_POS / IN3_NEG: Positive / Negative Input Clock 3
I
PECL/LVDS This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
IN4_POS / IN4_NEG: Positive / Negative Input Clock 4
I
PECL/LVDS This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
IN5_POS / IN5_NEG: Positive / Negative Input Clock 5
I
PECL/LVDS This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
IN6_POS / IN6_NEG: Positive / Negative Input Clock 6
I
PECL/LVDS This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
I
pull-down
CMOS
IN7: Input Clock 7
This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
I
pull-down
CMOS
IN8: Input Clock 8
This pin can also be used as a sync input, and in this case a 2 kHz, 4 kHz, 8 kHz, or 1PPS
signal can be input on this pin.
REVISION 1 09/23/14
5
PORT SYNCHRONIZER FOR IEEE 1588 AND
10G/40G SYNCHRONOUS ETHERNET