82P33724 Datasheet, PDF (6/13 Pages) Integrated Circuit Systems – Differential reference inputs

82P33724 SHORT FORM DATA SHEET
Table 1: Pin Description (Continued)
Pin No.
30
28
25
26
21
22
71
70
68
67
65
63
61
60
13
1
54
56
55
57
46
45
Name
OUT1
OUT2
OUT3_POS
OUT3_NEG
OUT4_POS
OUT4_NEG
OUT5_POS
OUT5_NEG
OUT6_POS
OUT6_NEG
OUT7
OUT8
OUT9
OUT10
VC1
VC2
DPLL3_LOCK
DPLL2_LOCK
DPLL1_LOCK
INT_REQ
MPU_MODE1/
I2CM_SCL
MPU_MODE0/
I2CM_SDA
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
Tri-state
I/O
pull-up
Type
Description
CMOS
Output Clock
OUT1 ~ OUT2: Output Clock 1 ~ 2
PECL/LVDS
OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
PECL/LVDS
OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
PECL/LVDS
OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
PECL/LVDS
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
CMOS ^{OUT7 ~ OUT8: Output Clock 7 ~ 8}
CMOS ^{OUT9 ~ OUT10: Output Clock 9 ~ 10}
Analog
Analog
Miscellaneous
VC1: APLL1 VC Output
An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in
parallel) should be connected to this pin.
VC2: APLL2 VC Output
An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in
parallel) should be connected to this pin.
Lock Signal
CMOS
CMOS
DPLL3_LOCK
This pin goes high when DPLL3 is locked
DPLL2_LOCK
This pin goes high when DPLL2 is locked
CMOS
DPLL1_LOCK
This pin goes high when DPLL1 is locked
Microprocessor Interface
CMOS
INT_REQ: Interrupt Request
This pin is used as an interrupt request.
MPU_MODE[1:0]: Microprocessor Interface Mode Selection
During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol-
lows:
00: I2C mode
CMOS/
Open Drain
01: SPI mode
10: UART mode
11: I2C master (EEPROM) mode
I2CM_SCL: Serial Clock Line
In I2C master mode, the serial clock is output on this pin.
I2CM_SDA: Serial Data Input for I2C Master Mode
In I2C master mode, this pin is used as the for the serial data.
PORT SYNCHRONIZER FOR IEEE 1588 AND
6
SYNCHRONOUS ETHERNET
REVISION 1 09/23/14