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82P33724 Datasheet, PDF (3/13 Pages) Integrated Circuit Systems – Differential reference inputs
FUNCTIONAL BLOCK DIAGRAM
LOS0 / XO_FREQ0
LOS1 / XO_FREQ1
LOS2 / XO_FREQ2
LOS3
System Clock
SYS PLL
APLL1
IN1(P/N)
IN2(P/N)
IN3(P/N)
IN4(P/N)
IN5
IN6
Reference
monitors
Reference
selection
Frac-N input
dividers
DPLL1
DPLL2
APLL2
ex_sync module
DPLL3
I2C Master Control and
I2C Slave,
SPI, UART
Status
Registers
JTAG
Figure 1. Functional Block Diagram
82P33724 SHORT FORM DATA SHEET
OutDiv
OutDiv
OutDiv
OutDiv
OutDiv
OutDiv
OutDiv
OutDiv
OUT1
OUT2
OUT3p/n
OUT4p/n
OUT5p/n
OUT6p/n
OUT7
OUT8
OutDiv
OutDiv
OUT9
OUT10
FRSYNC_8K_1PPS
MFRSYNC_2K_1PPS
REVISION 1 09/23/14
3
PORT SYNCHRONIZER FOR IEEE 1588 AND
SYNCHRONOUS ETHERNET