82P33724 Datasheet, PDF (2/13 Pages) Integrated Circuit Systems – Differential reference inputs

82P33724 SHORT FORM DATA SHEET
DESCRIPTION
The 82P33724 Port Synchronizer for IEEE 1588 and Synchronous Ethernet provides tools to manage timing references, clock conversion and tim-
ing paths for IEEE 1588 and Synchronous Ethernet (SyncE). The device supports up to three independent timing paths for: IEEE 1588 clock genera-
tion; SyncE clock generation; and general purpose frequency translation. The device outputs low-jitter clocks that can directly synchronize Ethernet
interfaces; as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).
The 82P33724 accepts four differential reference inputs and two single ended reference inputs that can operate at common Ethernet, SONET/
SDH and PDH frequencies that range from 2 kHz to 650 MHz. The references are continually monitored for loss of signal and for frequency offset per
user programmed thresholds. All of the references are available to all three Digital PLLs (DPLLs). The active reference for each DPLL is determined
by forced selection or by automatic selection based on user programmed priorities, locking allowances, reference monitors, and LOS inputs.
The 82P33724 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1/DPLL2 can lock to the clock reference
and align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended reference
inputs to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync signals
can have a frequency of 1 PPS, 2 kHz, 4kHz or 8 kHz. This feature enables DPLL1/DPLL2 to phase align its frame sync and multi-frame sync outputs
with a sync input without the need use a low bandwidth setting to lock directly to the sync input.
The DPLLs support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode the DPLLs synthesize clocks based on
the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term output fre-
quency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses frequency data
acquired while in Locked mode to generate accurate frequencies when input references are not available.
The 82P33724 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock deter-
mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the
DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked mode.
DPLL1 and DPLL2 can be configured with a range of selectable filtering bandwidths from 18 Hz to 567 Hz. DPLL3 is a wideband (BW > 25Hz) fre-
quency translator that can be used, for example, to convert a recovered SyncE clock to a 25MHz backplane clock.
Clocks generated by DPLL1 and DPLL2 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The
output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces, and for IEEE 1588 time stamps clocks and 1 PPS
signals.
All 82P33724 control and status registers are accessed through an I2C slave, SPI or the UART microprocessor interface. For configuring the
DPLLs, APLL1 and APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset.
PORT SYNCHRONIZER FOR IEEE 1588 AND
2
SYNCHRONOUS ETHERNET
REVISION 1 09/23/14