ICSSSTV16859 Datasheet, PDF (5/8 Pages) Integrated Circuit Systems – DDR 13-Bit to 26-Bit Registered Buffer

ICSSSTV16859
Preliminary Product Preview
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
SYM B OL
PAR AM ETER S
V_DD = 2.5V ±0.2V
M IN M AX
f_clock Clock frequency
200
t_PD Clock to output time
TBD
t_RST Reset to output time
5
t_SL Output slew rate
1
4
t_SU
Setup time, fast slew rate ^{2, 4}
Setu p time, slo w slew rate ^{3, 4}
Data before CK_↑ , CK#_↓
0 .7 5
0 .9
Ho ld time, fast slew rate ^{2, 4}
0 .7 5
T_h
Hold time, slow slew rate ^{3, 4 Data after CK↑ , CK#↓}
0 .9
Note s:
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate_=≥ 1V/ns.
3 - For data signal input slew rate_=≥=0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rates are_=≥=1V/ns.
UNITS
MHz
ns
ns
V/ns
ns
ns
ns
ns
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
SYM B OL
Fro m
(In p u t )
To
(Ou t p u t )
V_DD = 2.5V ±0.2V
UNITS
M IN
TYP MAX
fmax
200
M Hz
t_PD CLK, CLK#
Q
1 .1
2 .8
ns
t_ph1 CLK, CLK#
Q
5
ns
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