ICSSSTV16859 Datasheet, PDF (1/8 Pages) Integrated Circuit Systems – DDR 13-Bit to 26-Bit Registered Buffer

Integrated
Circuit
Systems, Inc.
ICSSSTV16859
Preliminary Product Preview
DDR 13-Bit to 26-Bit Registered Buffer
Recommended Application:
DDR Memory Modules
Product Features:
• Differential clock signals
• Meets SSTL_2 signal data
• Supports SSTL_2 class II specifications on outputs
• low-voltage operation
- VDD = 2.3V to 2.7V
• Available in 64 pin TSSOP and 56 pin MLF2 packages
Truth Table¹
RESET#
L
H
H
H
Inputs
CLK
CLK#
X or
Floating
­
­
X or
Floating
¯
¯
L or H L or H
D
X or
Floating
H
L
X
Q Outputs
Q
L
H
L
Q₀₍₂₎
Notes:
1. H = High Signal Level
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH -to LOW
X = Irrelevant
2. Output level before the indicated
steady state input conditions were
established.
CLK
CLK#
48
49
RESET# ⁵¹
D1
VREF
35
45
Block Diagram
R
CLK
D1
16 _Q1A
32 _Q1B
To 12 Other Channels
Pin Configurations
Q13A
1
Q12A
2
Q11A
3
Q10A
4
Q9A
5
VDDQ
6
GND
7
Q8A
8
Q7A
9
Q6A
10
Q5A
11
Q4A
12
Q3A
13
Q2A
14
GND
15
Q1A
16
Q13B
17
VDDQ
18
Q12B
19
Q11B
20
Q10B
21
Q9B
22
Q8B
23
Q7B
24
Q6B
25
GND
26
VDDQ
27
Q5B
28
Q4B
29
Q3B
30
Q2B
31
Q1B
32
64
VDDQ
63
GND
62
D13
61
D12
60
VDD
59
VDDQ
58
GND
57
D11
56
D10
55
D9
54
GND
53
D8
52
D7
51
RESET#
50
GND
49
CLK#
48
CLK
47
VDDQ
46
VDD
45
VREF
44
D6
43
GND
42
D5
41
D4
40
D3
39
GND
38
VDDQ
37
VDD
36
D2
35
D1
34
GND
33
VDDQ
64-Pin TSSOP
6.10 mm. Body, 0.50 mm. pitch
56
Q7A 1
Q6A
Q5A
Q4A
Q3A
Q2A
Q1A
Q13B
VDDQ
Q12B
Q11B
Q10B
Q9B
Q8B14
15
ICSSTV16859
43
42 D10
D9
D8
D7
RB
GND
CLKB
CLK
VDDQ
VDDI
VREF
D6
D5
29 D4
28
56 pin MLF2
16859 Rev B 06/22/01
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PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.