ICS952606 Datasheet, PDF (5/20 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
Absolute Max
Symbol
Parameter
VDD_A
3.3V Core Supply Voltage
VDD_In 3.3V Logic Input Supply Voltage
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
ESD prot
human body model
Min
-0.5
-65
0
2000
Max
V_{DD +} 0.5V
V_{DD +} 0.5V
150
70
115
Units
V
V
°C
°C
°C
V
ICS952606
Electrical Characteristics - Input/Supply/Common Output Parameters
T_A = 0 - 70°C; Supply Voltage V_DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
MAX UNITS NOTES
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V_IH
3.3V +/-5%
2
V_IL
3.3V +/-5%
V_SS -
0.3
I_IH
V_IN = V_DD
-5
I_IL1
V_IN = 0 V; Inputs with no pull-up _-5
resistors
I_IL2
V_IN = 0 V; Inputs with pull-up
resistors
-200
V_DD + 0.3 V
0.8
V
5
uA
uA
uA
Operating Supply Current I_DD3.3OP
Full Active, C_L = Full load;
260.000 350
Powerdown Current
I_DD3.3PD
all diff pairs driven
all differential pairs tri-stated
31.000
35
0.300
12
Input Frequency³
F_i
Pin Inductance¹
L_pin
V_DD = 3.3 V
14.31818
7
C_IN
Logic Inputs
5
Input Capacitance¹
C_OUT
Output pin capacitance
6
C_INX
X1 & X2 pins
5
Clk Stabilization^1,2
T_STAB
From VDD Power-Up or de-
assertion of PD# to 1st clock.
1.8
Modulation Frequency
Triangular Modulation
30
33
Tdrive_PD#
CPU output enable after
PD# de-assertion
300
Tfall_Pd#
PD# fall time of
5
Trise_Pd#
PD# rise time of
5
1_{Guaranteed by design, not 100% tested in production.}
2_{See timing diagrams for timing requirements.}
3 _{Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet}
ppm frequency accuracy on PLL outputs.
mA
mA
mA
MHz 3
nH
1
pF
1
pF
1
pF
1
ms 1,2
kHz
1
us
1
ns
1
ns
2
0717F—06/10/05
5