ICS952606 Datasheet, PDF (3/20 Pages) Integrated Circuit Systems – Programmable Timing Control Hub for Next Gen P4 processor

Integrated
Circuit
Systems, Inc.
ICS952606
Pin Description (Continued)
PIN #
PIN NAME
30 3V66_0
25 3V66_3/VCH
26 3V66_2
27 VDD3V66
28 GND
29 3V66_1
30 3V66_0
31 SCLK
32 SDATA
33 Vtt_Pwrgd#
34 VDD
35 SRCCLKC
36 SRCCLKT
37 GND
38 CPUCLKC0
39 CPUCLKT0
40 VDDCPU
41 CPUCLKC1
42 CPUCLKT1
43 GND
44 CPUCLKC_ITP
45 CPUCLKT_ITP
46 IREF
47 GND
48 VDDA
PIN TYPE
DESCRIPTION
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
IN
PWR
OUT
OUT
PWR
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output / 48MHz VCH clock output.
3.3V 66.66MHz clock output
Power pin for the 3.3V 66MHz clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
OUT
PWR
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
OUT
PWR
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
OUT
OUT
PWR
PWR
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin.
3.3V power for the PLL core.
0717F—06/10/05
3