ICS951901 Datasheet, PDF (5/19 Pages) Integrated Circuit Systems – Programmable Frequency Generator & Integrated Buffers for Pentium III Processor

ICS951901
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 2,3 0 REF strength 0=1X, 1=2X
Bit6 45
CPUCLK2 - Stop - Control
0 0=CPU_STOP# will control CPUCLK2,
1=CPUCLK2 is free running even if CPU_STOP# is low
Bit5 -
X AGPSEL (Readback)
Bit4 -
X MODE (Readback)
Bit3 -
X CPU_STOP# (Readback)
Bit2 -
X PCI_STOP# (Readback)
Bit1 -
X SDRAM_STOP# (Readback)
Bit0 -
AGP Speed Toggle
0 0=AGPSEL (pin2) will be determined by latch input setting,
1=AGPSEL will be opposite of latch input setting
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
0 Reserved
0 Reserved
1 Reserved
0 Reserved
1 Reserved
0 Reserved
0 Reserved
1 Reserved
Byte 8: Byte Count and Read Back Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
-
-
-
-
PWD
DESCRIPTION
0 Reserved
0 Reserved
0 Reserved
0 Reserved
0 Reserved
1 Reserved
0 Reserved
0 Reserved
Byte 9: Watchdog Timer Count Register
Bit PWD
Description
Bit 7 0
Bit 6 0 The decimal representation of these
Bit 5 0 ^{8 bits correspond to 290ms or 1ms}
Bit 4
Bit 3
1
0
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
Bit 2 0 _{at power up is 16X 290ms = 4.6}
Bit 1 0 seconds.
Bit 0 0
0670B—07/15/04
Byte 10: VCO Control Selection Bit &
Watchdog Timer Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
0
0
0
0
0
0
Description
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
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