ICS951901 Datasheet, PDF (13/19 Pages) Integrated Circuit Systems – Programmable Frequency Generator & Integrated Buffers for Pentium III Processor

ICS951901
Brief I²C registers description for ICS951901
Programmable System Frequency Generator
Register Name
Functionality &
Frequency Select
Register
Byte
0
Output Control Registers 1-6
Vendor ID & Revision ID
Registers
7
Byte Count
Read Back Register
8
Watchdog Timer
Count Register
9
Description
Output frequency, hardware / I²C
frequency select, spread spectrum &
output enable control register.
Active / inactive output control
registers/latch inputs read back.
Byte 11 bit[7:4] is ICS vendor id -
1001. Other bits in this register
designate device revision ID of this
part.
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00_H to
this byte.
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
PWD Default
See individual
byte
description
See individual
byte
description
See individual
byte
description
08_H
10_H
Watchdog Control
Registers
10 Bit [6:0]
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
000,0000
This bit select whether the output
VCO Control Selection _{10 Bit [7]} frequency is control by
0
Bit
hardware/byte 0 configurations or
byte 11&12 programming.
VCO Frequency Control
Registers
11-12
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
Depended on
hardware/byte
0 configuration
Notes:
Spread Spectrum
Control Registers
Group Skews Control
Registers
Output Rise/Fall Time
Select Registers
13-14
15-16
17-20
These registers control the spread
percentage amount.
Increment or decrement the group
skew amount as compared to the
initial skew.
These registers will control the
output rise and fall time.
Depended on
hardware/byte
0 configuration
See individual
byte
description
See individual
byte
description
1.
The ICS clock generator is a slave/receiver, I²C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
2. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
3. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4. The input is operating at 3.3V logic levels.
5. The data byte format is 8 bit bytes.
6.
To simplify the clock generator I²C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
7. At power-on, all registers are set to a default condition, as shown.
0670B—07/15/04
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