ICS93716 Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – Low Cost DDR Phase Lock Loop Clock Driver

ICS9371 6
DC Electrical Characteristics (see note1)
T_A = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Supply Voltage
Low level input voltage
V_DDQ, A_VDD
2.3
CLK_INT, CLK_INC, FB_INC,
V_IL FB_INT
SCLK, SDATA
-0.3
High level input voltage
V_IH
CLK_INT, CLK_INC, FB_INC,
FB_INT
V_DD/2 + 0.18
SCLK, SDATA
1.7
DC input signal voltage
(note 2)
V_IN
-0.3
Differential input signal
voltage (note 3)
DC - CLK_INT, CLK_INC,
0.36
V_ID
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
0.7
FB_INC, FB_INT
Output differential cross-
voltage (note 4)
V_OX
V_DD/2 - 0.15
Input differential cross-
voltage (note 4)
V_IX
V_DD/2 - 0.2
High Impedance
Output Current
I_OZ
V_DD=2.7V, V_OUT=V_DD or GND
Operating free-air
temperature
T_A
0
TYP
2.5
0.4
2.1
V_DD/2
0.1
MAX
2.7
UNITS
V
V_DD/2 - 0.18 V
0.7
V
V
5
V
V_DD + 0.3
V
V_DD + 0.6
V
V_DD + 0.6
V
V_DD/2 + 0.15 V
V_DD/2 + 0.2 V
±5
µA
85
°C
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC excursion of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of V_DD and is the
voltage at which the differential signal crosses.
0420E—04/01/03
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