ICS93716 Datasheet, PDF (1/12 Pages) Integrated Circuit Systems – Low Cost DDR Phase Lock Loop Clock Driver

Integrated
Circuit
Systems, Inc.
ICS9371 6
Low Cost DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
Product Description/Features:
• Low skew, low jitter PLL clock driver
• I²C for functional and output control
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
Switching Characteristics:
• PEAK - PEAK jitter (66MHz): <120ps
• PEAK - PEAK jitter (>100MHz): <75ps
• CYCLE - CYCLE jitter (>100MHz):<65ps
• OUTPUT - OUTPUT skew: <100ps
• Output Rise and Fall Time: 650ps - 950ps
Pin Configuration
CLKC0
1
CLKT0
2
VDD
3
CLKT1
4
CLKC1
5
GND
6
SCLK
7
CLK_INT
8
CLK_INC
9
VDDA 10
GND 11
VDD 12
CLKT2 13
CLKC2 14
28 GND
27 CLKC5
26 CLKT5
25 CLKC4
24 CLKT4
23 VDD
22 SDATA
21 FBINC
20 FBINT
19 FB_OUTT
18 FB_OUTC
17 CLKT3
16 CLKC3
15 GND
28-Pin SSOP and TSSOP
Block Diagram
Functionality
AVDD
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
GND
GND
INPUTS
CLK_INT CLK_INC
L
H
H
L
<20MHz
L
H
H
L
CLKT
L
H
Z
L
H
OUTPUTS
CLKC FB_OUTT
H
L
L
H
Z
Z
H
L
L
H
PLL State
FB_OUTC
H
on
L
on
Z
off
H
Bypassed/off
L
Bypassed/off
SCLK
SDATA
Control
Logic
FB_INT
FB_INC
PLL
CLK_INC
CLK_INT
0420E—04/01/03
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5