ICS9250-09 Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – Frequency Timing Generator for PENTIUM II Systems

ICS9250-09
PCI_STOP# Timing Diagram
PCI_STOP# is an input to the clock synthesizer and must be made synchronous to the clock driver PCICLK_F output. It is used
to turn off the PCI clocks for low power operation. PCI clocks are required to be stopped in a low state and started such that a
full high pulse width is guaranteed. ONLY one rising edge of PCICLK_F is allowed after the clock control logic switched for the
PCI outputs to become enabled/disabled.
Notes:
1. All timing is referenced to CPUCLK.
2. PCI_STOP# signal is an input signal which must be made synchronous to PCICLK_F output.
3. Internal means inside the chip.
4. All other clocks continue to run undisturbed.
5. PD# and CPU_STOP# are shown in a high state.
6. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
5