ICS9250-09 Datasheet, PDF (11/12 Pages) Integrated Circuit Systems – Frequency Timing Generator for PENTIUM II Systems

ICS9250-09
General Layout Precautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
by traces.
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
Notes:
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistor. Not shown in all
places to improve readability of
diagram.
2 Optional crystal load capacitors are
recommended. They should be
included in the layout but not inserted
unless needed.
Connections to VDD:
VDD
Ferrite
Bead
C2
22µF/20V
Tantalum
C2
22µF/20V
Tantalum
Ferrite
Bead
VDD
1
2
3
4
C1
5
C1
6
2
7
8
9
10
11
12
3.3V Power Route
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
C3
40
39
38
37
36
35
34
33
32
31
30
29
2.5V Power Route
1
Clock Load
3.3V Power Route
= Routed Power
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
11