ICS9248-114 Datasheet, PDF (5/14 Pages) Integrated Circuit Systems – AMD - K7™ System Clock Chip

ICS9248-114
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
-
-
40
-
43,44
46
PWD
DESCRIPTION
X FS2#
1 (Reserved)
1 (Reserved)
X FS3#
1 SDRAM_OUT
X (SEL24_48#)#
CPUCLK0 enable (both
1 differential pair. "True" and
Complimentary")
1 CPUCLKT enable
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
7
-
13
12
11
10
8
PWD
DESCRIPTION
X FS0#
1 PCICLK_F
1 (Reserved)
1 PCICLK4
1 PCICLK3
1 PCICLK2
1 PCICLK1
1 PCICLK0
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
-
-
26
25
17
18
20
21
PWD
DESCRIPTION
1 (Reserved)
1 (Reserved)
1 48MHz
1 24_48MHz
1 SDRAM 11
1 SDRAM 10
1 SDRAM 9
1 SDRAM 8
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
28
29
31
32
34
35
37
38
PWD
DESCRIPTION
1 SDRAM 7
1 SDRAM 6
1 SDRAM 5
1 SDRAM 4
1 SDRAM 3
1 SDRAM 2
1 SDRAM 1
1 SDRAM 0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
-
1 (Reserved)
-
1 (Reserved)
-
1 (Reserved)
-
X MODE#
-
X FS1#
-
1 (Reserved)
48
1 REF1
2
1 REF0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit7 -
0 Reserved (Note)
Bit6 -
0 Reserved (Note)
Bit5 -
0 Reserved (Note)
Bit4 -
0 Reserved (Note)
Bit3 -
0 Reserved (Note)
Bit2 -
1 Reserved (Note)
Bit1 -
1 Reserved (Note)
Bit0 -
0 Reserved (Note)
Note: Don’t write into this register, writing into this
register can cause malfunction
Third party brands and names are the property of their respective owners.
5