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ICS9248-114 Datasheet, PDF (4/14 Pages) Integrated Circuit Systems – AMD - K7™ System Clock Chip
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ICS9248-114
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 2,
Bit 7:4
Bit 3
Bit 1
Bit 0
Description
Bit (2, 7, 6, 5, 4)
CPUCLK
(MHz)
PCICLK
(MHz)
00000
124.00
41.33
0000 1
75.00
37.50
000 10
83.30
41.65
000 11
66.80
33.40
00 100
103.00
34.33
00 10 1
112.00
37.33
00 110
133.30
44.43
00 111
100.00
33.33
0 1000
120.00
40.00
0 100 1
115.00
38.33
0 10 10
110.00
36.67
0 10 11
105.00
35.00
0 1100
140.00
35.00
0 110 1
150.00
37.50
0 1110
124.00
31.00
0 1111
133.30
33.33
10 0 0 0
90.00
30.00
1000 1
92.50
30.83
100 10
95.00
31.67
100 11
97.50
32.50
10 100
101.50
33.83
10 10 1
127.00
42.33
10 110
136.50
34.13
10 111
100.00
33.33
1 10 0 0
120.00
40.00
1100 1
117.50
39.17
110 10
122.00
40.67
110 11
107.50
35.83
1 1 10 0
145.00
36.25
1110 1
155.00
38.75
1 1 1 10
130.00
32.50
11111
133.30
33.32
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Spread
Precentage
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
-0.5% Down Spread
-0.5% Down Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
±0.25% Center Spread
-0.5% Down Spread
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I2C readback of the power up default could indicate the manufacture ID in bits 2, 7:4 as shown.
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4
PWD
00100
Note1
0
1
0
 ▷