ICS9148-111 Datasheet, PDF (5/18 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM/ProTM

ICS9148-111
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Bit 7
Bit 6:4
Bit 3
Bit 2
Bit 1
Bit 0
Description
Must be 0 for normal operation
0 -- +/- 0.25% Spread Spectrum Modulation
1 -- +/- 0.6% Spread Spectrum Modulation
Bit6 Bit5 Bit4
111
110
101
100
CPU Clock
100
95.25
83.3
75
PCI
33.33
31.75
33.30
30.00
011
91.5
30.50
010
96.22
32.07
001
66.8
33.40
000
60
30.00
0 - Frequency is selected by hardware select, Latched inputs
1 - Frequency is selected by Bit 6:4 (above)
Must be 0 for normal operation
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1 - Tristate all outputs
AGP
66.67
63.50
66.60
60.00
61.00
64.15
66.80
60.00
PWD
0
Note 1
0
0
0
0
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 000, and if
bit 3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle.
Note: PWD = Power-Up Default
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
40
-
41
43
44
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
(Reserved)
(Reserved)
SDRAM12 (Act/Inact)
(Reserved)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
7
-
13
12
11
10
8
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
PCICLK_F (Act/Inact)
(Reserved)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Third party brands and names are the property of their respective owners.
5