ICS9148-111 Datasheet, PDF (17/18 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM/ProTM

ICS9148-111
General Layout Precautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
VDD
by traces.
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
Notes:
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistor. Not shown in all
places to improve readability of
diagram.
2 Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
Component Values:
C1 : Crystal load values determined by user
C2 : 22µF/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 15pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0.01µF ceramic
Connections to VDD:
Ferrite
Bead
C2
22µF/20V
Tantalum
2
C1
C1
3.3V Power Route
1
48
2
47
3
46
C2
22µF/20V
Ferrite
Bead
Tantalum
4
45
VDD
5
44
6
43
7
42
2.5V Power Route
8
41
9
40
10
39
Ground
11
38
12
37
13
36
14
35
15
34
16
33
3.3V Power Route
17
32
18
31
19
30
1
20
29
Clock Load
C3
21
28
22
27
23
26
24
25
= Routed Power
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
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