ICS9148-111 Datasheet, PDF (2/18 Pages) Integrated Circuit Systems – Frequency Generator & Integrated Buffers for PENTIUM/ProTM

ICS9148-111
Pin Configuration
PIN NUMBER
1
2
3,9,16,22,27,
33,39,45
4
PIN NAME
VDD1
REF0
CPU3.3#_2.5^1,2
GND
X1
5
6
7
8
10, 11, 12, 13
14
15
17
18
28, 29, 31, 32, 34,
35,37,38
20
21
19,30,36
23
24
25
26
41, 43, 44
40
42
46, 47
48
X2
VDD2
PCICLK_F
FS1^{1, 2}
PCICLK0
FS2^{1, 2}
PCICLK(1:4)
VDD5
BUFFERIN
CPU_STOP#¹
SDRAM 11
PCI_STOP#¹
SDRAM 10
SDRAM (0:9)
AGP_STOP#
SDRAM9
PD#
SDRAM8
VDD3
SDATA
SCLK
AGP0
MODE^{1, 2}
48MHz
FS0^{1, 2}
CPUCLK(0:3)
SDRAM12
VDDL
AGP (1:2)
VDD4
TYPE
PWR
OUT
IN
PWR
IN
OUT
PWR
OUT
IN
OUT
IN
OUT
PWR
IN
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
PWR
IN
IN
OUT
IN
OUT
IN
OUT
OUT
PWR
OUT
PWR
DESCRIPTION
Ref (0:2), XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.
Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V
CPU¹. Latched input²
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (33pF)
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew
(CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Supply for fixed PLL, 48MHz, AGP0
Input pin for SDRAM buffers.
Halts CPUCLK (0:3) clocks at logic 0 level, when input low (in Mobile
Mode, MODE=0)
SDRAM clock output
Halts PCICLK(0:5) clocks at logic 0 level, when input low (In mobile mode,
MODE=0)
SDRAM clock output
SDRAM clock outputs.
This asynchronous input halts AGP(1:2) clocks at logic "0" level when input
low (in Mobile Mode, MODE=0) Does not affect AGP0
SDRAM clock output
This asyncheronous Power Down input Stops the VCO, crystal & internal
clocks when active, Low. (In Mobile Mode, MODE=0)
SDRAM clock output
Supply for SDRAM (0:11), CPU Core, 48MHz clocks,
nominal 3.3V.
Data input for I²C serial input.
Clock input of I²C input
Advanced Graphic Port output, powered by VDD4. Not affected by
AGP_STOP#
Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock for USB timing.
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
Feedback SDRAM clock output.
Supply for CPU (0:3), either 2.5V or 3.3V nominal
Advanced Graphic Port outputs, powered by VDD4.
Supply for AGP (0:2)
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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