ICS8543 Datasheet, PDF (5/7 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8543
LOW SKEW, 1-TO-4
LVDS FANOUT BUFFER
TABLE 4D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C
Symbol
VIH
VIL
IIH
IIL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
CLK_EN, CLK_SEL, OE
CLK_EN, CLK_SEL, OE
CLK_EN, OE
CLK_SEL
CLK_EN, OE
CLK_SEL
Test Conditions
Minimum
2
-150
-5
Typical
Maximum
0.8
5
150
Units
V
V
µA
µA
µA
µA
TABLE 4E. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C
Symbol
VOD
∆ VOD
VOS
∆ VOS
IOZ
IOFF
IOSD
IOS
Parameter
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
High Impedance Leakage Current
Power Off Leakage
Differential Output Short Circuit Current
Output Short Circuit Current
Test Conditions
Minimum
250
1.125
-10
-20
Typical
350
4
1.25
5
±1
±1
3.0
3.0
Maximum
450
35
1.375
25
+10
+20
Units
mV
mV
V
mV
µA
µA
mA
mA
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V±5%, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
fMAX
Maximum Input Frequency
650
tpLH
Propagation Delay, Low-to-High 0 ≤ f ≤ 650MHz
1.8
2.4
tsk(o)
Output Skew; NOTE 2
50
tsk(pp) Part-to-Part Skew; NOTE 3
300
tR
Output Rise Time
tF
Output Fall Time
tPW
Output Pulse Width
R_L = 100Ω
200
400
600
R_L = 100Ω
200
400
600
tCYCLE/2 - TBD
tCYCLE/2 + TBD
tEN
Output Enable Time
TBD
tDIS
Output Disable Time
TBD
NOTE 1: All parameters measured at fMAX unless noted otherwise.
NOTE 2: Defined as skew across outputs at the same supply voltages and with equal load conditions.
Measured from the 50% point of the input to the differential output crossing point.
NOTE 3: Defined as skew at different outputs on different devices operating at the same supply voltages
and with equal load conditions. Measured from 50% of like inputs to the differential output crossing point.
Units
MHz
ns
ps
ps
ps
ps
ns
ns
ns
ICS8543BG
www.icst.com/products/hiperclocks.html
5
REV. C MAY 21, 2001