ICS8543 Datasheet, PDF (3/7 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8543
LOW SKEW, 1-TO-4
LVDS FANOUT BUFFER
TABLE 3A. CONTROL INPUTS FUNCTION TABLE
Inputs
Outputs
OE
CLK_EN
CLK_SEL
Q1 thru Q3
nQ1 thru nQ3
0
X
X
Hi Z
Hi Z
1
0
0
Low
1
0
1
Low
High
High
1
1
0
ACTIVE
ACTIVE
1
1
1
ACTIVE
ACTIVE
In the active mode the state of the output is a function of the HCLK, nHCLK and PCLK, nPCLK inputs as described in
Table 3B.
TABLE 3B. CLOCK INPUTS FUNCTION TABLE
Inputs
HCLK, PCLK nHCLK, nPCLK
Outputs
Q0 thru Q3
nQ0 thru nQ3
Input to Output Mode
Polarity
0
1
LOW
HIGH
Differential to Differential
Non Inverting
1
0
HIGH
LOW
Differential to Differential
Non Inverting
0
Biased; NOTE 1
LOW
HIGH
Single Ended to Differential Non Inverting
1
Biased; NOTE 1
HIGH
LOW
Single Ended to Differential Non Inverting
Biased; NOTE 1
0
HIGH
LOW
Single Ended to Differential
Inverting
Biased; NOTE 1
1
LOW
HIGH
Single Ended to Differential
Inverting
NOTE 1: Single ended use requires that one of the differential inputs be biased. The voltage at the biased input sets the
switch point for the single ended input. For LVCMOS and LVTTL levels the recommended input bias network is a resistor to
VCC, a resistor of equal value to ground and a 0.1µF capacitor from the input to ground. The resulting switch point is
approximately VCC/2 ± 300mV.
ICS8543BG
www.icst.com/products/hiperclocks.html
3
REV. C MAY 21, 2001