ICS8543 Datasheet, PDF (2/7 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-4 LVDS FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS8543
LOW SKEW, 1-TO-4
LVDS FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 9, 13
Name
VEE
2
CLK_EN
3
4
5
6
7
8
10, 18
11, 12
14, 15
16, 17
19, 20
CLK_SEL
HCLK
nHCLK
PCLK
nPCLK
OE
VDD
nQ3, Q3
nQ2, Q2
nQ1, Q1
nQ0, Q0
Type
Power
Input
Pullup
Input Pulldown
Input
Input
Input
Input
Input
Power
Output
Output
Output
Output
Pulldown
Pullup
Pulldown
Pullup
Pullup
Description
Power supply ground. Connect to ground.
Synchronous clock enable. When HIGH clock outputs follows clock
input. When LOW, Q outputs are force low, nQ outputs are force high.
LVCMOS / LVTTL interface levels.
Clock select input. When HIGH selects differential PECL inputs.
When LOW selects differential HSTL inputs.
LVCMOS / LVTTL interface levels.
Non-inverting differential HSTL clock input.
Inverting differential HSTL clock input.
Non-inverting differential PECL clock input.
Inverting differential PECL clock input.
Output enable. Controls enabling and disabling of outputs Q0, nQ0
thru Q3, nQ3
Power supply pin. Connect to 3.3V.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
Differential clock outputs. LVDS interface levels.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
RPULLUP
RPULLDOWN
Parameter
HCLK, nHCLK
Input Capacitance ^{PCLK, nPLCK}
CLK_EN,
CLK_SEL
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
51
51
Maximum
4
4
Units
pF
pF
4
pF
KΩ
KΩ
ICS8543BG
www.icst.com/products/hiperclocks.html
2
REV. C MAY 21, 2001