ICS8521 Datasheet, PDF (5/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8521
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, V_DD = 3.3V±5%, V_DDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
PCLK
I_IH
Input High Current
nPCLK
V_DD = V_IN = 3.465V
V_DD = V_IN = 3.465V
PCLK
I_IL
Input Low Current
nPCLK
V_DD = 3.465V, V_IN = 0V
V_DD = 3.465V, V_IN = 0V
-5
-150
V
Peak-to-Peak Input Voltage
0.3
PP
V_CMR
Common Mode Input Voltage;
NOTE 1, 2
1.5
NOTE 1: Common mode voltage is defined as V_IH.
NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is V_DD + 0.3V.
Maximum
150
5
1
V_DD
Units
µA
µA
µA
µA
V
V
TABLE 4E. LVHSTL DC CHARACTERISTICS, V_DD = 3.3V±5%, V_DDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
V_OH
Output High Voltage;
NOTE 1
V_OL
Output Low Voltage;
NOTE 1
V_OX
V_SWING
Output Crossover Voltage
Peak-to-Peak
Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to ground.
Minimum
1.0
0
40% x (V_OH - V_OL) + V_OL
0.6
Typical
Maximum
1.2
0.4
60% x (V_OH - V_OL) + V_OL
1.1
Units
V
V
V
V
TABLE 5. AC CHARACTERISTICS, V_DD = 3.3V±5%, V_DDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
f_MAX
t_PD
tsk(o)
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 250MHz
1
tsk(pp) Part-to-Part Skew; NOTE 3, 4
t_R
Output Rise Time
t_F
Output Fall Time
odc
Output Duty Cycle
20% to 80% @ 50MHz
300
20% to 80% @ 50MHz
300
48
All parameters measured at 250MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
Measured from V_DD/2 to the output differential crossing point for single ended input levels.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differntial cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the output are measurd
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
500
1.8
50
250
700
700
52
Units
MHz
ns
ps
ps
ps
ps
%
8521BY
www.icst.com/products/hiperclocks.html
5
REV. B JULY 31, 2001