ICS8521 Datasheet, PDF (1/13 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8521
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8521 is a low skew, 1-to-9 3.3V Differ-
,&6
ential-to-LVHSTL Fanout Buffer and a member of
HiPerClockS™ _{the HiPerClockS™ family of High Performance}
Clock Solutions from ICS. The ICS8521 has two
selectable clock inputs. The CLK, nCLK pair can
accept most standard differential input levels. The PCLK,
nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The clock enable is internally synchronized to eliminate runt
pulseson the outputs during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8521 ideal for today’s
most advanced applications, such as IA64 and static RAMs.
FEATURES
• 9 LVHSTL outputs
• Selectable CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 500MHz
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 1.8ns (maximum)
• V_OH = 1.2V (maximum)
• 3.3V core, 1.8V output operating supply voltages
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK
nCLK
0
PCLK
nPCLK
1
CLK_SEL
D
Q
LE
PIN ASSIGNMENT
Q0
nQ0
32 31 30 29 28 27 26 25
VDD 1
24 VDDO
Q1
CLK 2
nQ1
nCLK 3
23 Q3
22 nQ3
Q2
nQ2
CLK_SEL 4
PCLK 5
ICS8521
21 Q4
20 nQ4
nPCLK 6
19 Q5
Q3
GND 7
nQ3
CLK_EN 8
18 nQ5
17 VDDO
Q4
9 10 1 1 12 13 14 1 5 16
nQ4
Q5
nQ5
Q6
nQ6
32-Lead LQFP
7mm x 7mm x 1.4mm Package Body
Q7
Y Package
nQ7
Top View
Q8
nQ8
8521BY
www.icst.com/products/hiperclocks.html
1
REV. B JULY 31, 2001