ICS840002I-01 Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER

Integrated
Circuit
Systems, Inc.
ICS840002I-01
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 5B. AC CHARACTERISTICS, V_DD = V_DDA = 3.3V±5%, V_DDO = 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
f_OUT
tsk(o)
tjit(Ø)
Output Frequency
Output Skew; NOTE 1, 3
RMS Phase Jitter (Random);
NOTE 2
Test Conditions
F_SEL[1:0] = 00
F_SEL[1:0] = 01
F_SEL[1:0] = 10 or 11
156.25MHz (1.875MHz - 20MHz)
125MHz (1.875MHz - 20MHz)
62.5MHz (1.875MHz - 20MHz)
Minimum
140
112
56
Typical
0.47
0.55
0.49
Maximum
175
140
68
12
Units
MHz
MHz
MHz
ps
ps
ps
ps
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
46
700
ps
54
%
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE
5C.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
V
DDO
=
2.5V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
F_SEL[1:0] = 00
140
175
f_OUT
Output Frequency
F_SEL[1:0] = 01
112
140
F_SEL[1:0] = 10 or 11
56
68
tsk(o) Output Skew; NOTE 1, 3
12
156.25MHz (1.875MHz - 20MHz)
0.49
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
125MHz (1.875MHz - 20MHz)
0.56
62.5MHz (1.875MHz - 20MHz)
0.52
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
700
46
54
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
MHz
MHz
ps
ps
ps
ps
ps
%
840002AGI-01
www.icst.com/products/hiperclocks.html
5
REV. A MARCH 3, 2005