ICS840002 Datasheet, PDF (5/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO LVCMOS/

Integrated
Circuit
Systems, Inc.
ICS840002I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
TABLE 6A. AC CHARACTERISTICS, V_DD = V_DDA = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
f_OUT
Output Frequency Range
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] = 11
46.67
tsk(o) Output Skew; NOTE 1, 3
212.5MHz @ Integration Range:
637KHz - 10MHz
0.83
159.375MHz @ Integration Range:
637KHz - 10MHz
0.62
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
156.25MHz @ Integration Range:
1.875MHz - 20MHz
0.59
106.25MHz @ Integration Range:
637KHz - 10MHz
0.80
53.125MHz @ Integration Range:
637KHz - 10MHz
0.68
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
F_SEL[1:0] ≠ 00
46
F_SEL[1:0] = 00
42
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
226.67
170
113.33
56.67
12
700
54
58
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
TABLE
6B.
AC
CHARACTERISTICS,
V
DD
=
V
DDA
=
3.3V±5%,
V
DDO
=
2.5V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical
F_SEL[1:0] = 00
186.67
f_OUT
Output Frequency Range
F_SEL[1:0] = 01
F_SEL[1:0] = 10
140
93.33
F_SEL[1:0] = 11
46.67
tsk(o) Output Skew; NOTE 1, 3
212.5MHz @ Integration Range:
637KHz - 10MHz
0.73
159.375MHz @ Integration Range:
637KHz - 10MHz
0.62
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 2
156.25MHz @ Integration Range:
1.875MHz - 20MHz
0.56
106.25MHz @ Integration Range:
637KHz - 10MHz
0.76
53.125MHz @ Integration Range:
637KHz - 10MHz
0.72
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
F_SEL[1:0] ≠ 00
46
F_SEL[1:0] = 00
42
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V_DDO/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Maximum
226.67
170
113.33
56.67
12
700
54
58
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
%
%
840002AGI
www.icst.com/products/hiperclocks.html
REV. A MARCH 10, 2005
5