ICS840002 Datasheet, PDF (10/13 Pages) Integrated Circuit Systems – FEMTOCLOCKS™ CRYSTAL-TO LVCMOS/

Integrated
Circuit
Systems, Inc.
ICS840002I
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL FREQUENCY SYNTHESIZER
LAYOUT GUIDELINE
Figure 3 shows a schematic example of the ICS840002I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18
pF parallel resonant 26.5625MHz crystal is used.The C1=22pF
and C2=22pF are recommended for frequency accuracy. For
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy. 1KΩ pullup or pulldown re-
sistors can be used for the logic control input pins.
Logic Control Input Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VDD
VD D A
R1
C3
10 10uF
C4
0.01u
U1
1
2
3
4
5
6
7
8
C6
0.1u
FSEL0
XTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
VDDA
VDD
ICS840002i
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
C2
tied to ground.
22pF
FSEL1
GN D
GN D
16
15
14
13
Q0 ₁₂
Q1
VD D O
XTAL_IN
XTAL_OUT
11
10
9
XTAL2
X1
XTAL1
C1
22pF
VD D
R2
33 Zo = 50 Ohm
LVCMOS
C5
0.1u
VDD
R3
100
Zo = 50 Ohm
R4
100
LVCMOS
Optional Termination
Unused output can be left floating. There should
no trace attached to unused output. Device
characterized with all outputs terminated.
FIGURE 3. ICS840002I SCHEMATIC EXAMPLE
840002AGI
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10
REV. A MARCH 10, 2005