ICS83940D Datasheet, PDF (5/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
TABLE 4B. DC CHARACTERISTICS, V_DD = 3.3V ± 5%, V_DDO = 2.5V ± 5%, TA = 0° TO 70°
Symbol Parameter
Test Conditions Minimum Typical
V_IH
V_IL
V_PP
V_CMR
Input High Voltage
LVCMOS_CLK
Input Low Voltage
LVCMOS_CLK
Peak-to-Peak Input Voltage PCLK, nPCLK
Input Common Mode Voltage;
NOTE 1, 2
PCLK, nPCLK
2.4
300
V_DD - 1.4
I_IN
Input Current
V_OH
Output High Voltage
I_OH = -20mA
1.8
V_OL
Output Low Voltage
I_OL = 20mA
I_DD
Core Supply Current
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is V_DD + 0.3V.
NOTE 2: Common mode voltage is defined as V_IH.
Maximum
V_DD
0.8
1000
V_DD - 0.6
±200
0.5
25
Units
V
V
mV
V
µA
V
V
mA
TABLE 5B. AC CHARACTERISTICS, V_DD = 3.3V ± 5%, V_DDO = 2.5V ± 5%, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
Output Frequency
PCLK, nPCLK;
t_pLH
Propagation Delay
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
1.7
1.7
PCLK, nPCLK;
t
Propagation Delay NOTE 1, 5
f > 150MHz
1.6
pLH
LVCMOS_CLK;
NOTE 2, 5
f > 150MHz
1.8
tsk(o)
Output Skew;
NOTE 3, 5
PCLK, nPCLK
LVCMOS_CLK
Measured on
rising edge @V_DDO/2
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f ≤ 150MHz
f ≤ 150MHz
250
MHz
3.2
ns
3.0
ns
3.4
ns
3.3
ns
150
ps
150
ps
1.5
ns
1.3
ns
tsk(pp)
Part-to-Part Skew;
NOTE 6
PCLK, nPCLK
LVCMOS_CLK
f > 150MHz
f > 150MHz
1.8
ns
1.5
ns
tsk(pp)
tjit
Part-to-Part Skew; ^{PCLK, nPCLK}
NOTE 4, 5
LVCMOS_CLK
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 7
Measured on
rising edge @V_DDO/2
850
ps
750
ps
0.03
ps
t /t
RF
odc
Output Rise/Fall Time
Output Duty Cycle
0.5 to 1.8V
f < 134MHz
0.3
1.2
ns
45
50
55
%
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output V_DDO/2.
NOTE 2: Measured from V_DD/2 to V_DDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 7: Driving only one input clock.
83940DY
www.icst.com/products/hiperclocks.html
REV. B JUNE 15, 2004
5