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ICS83940D Datasheet, PDF (1/15 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER | |||
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Integrated
Circuit
Systems, Inc.
ICS83940D
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS83940D is a low skew, 1-to-18 LVPECL-
ICS
to-LVCMOS/LVTTL Fanout Buffer and a member
HiPerClockS⢠of the HiPerClockSâ¢family of High Performance
Clock Solutions from ICS. The ICS83940D has
two selectable clock inputs. The PCLK, nPCLK
pair can accept LVPECL, CML, or SSTL input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed to
drive 50⦠series or parallel terminated transmission lines.
The ICS83940D is characterized at full 3.3V and 2.5V or mixed
3.3V core, 2.5V output operating supply modes. Guaranteed
output and part-to-part skew characteristics make the
ICS83940D ideal for those clock distribution applications
demanding well defined performance and repeatability.
FEATURES
⢠18 LVCMOS/LVTTL outputs
⢠Selectable LVCMOS_CLK or LVPECL clock inputs
⢠PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
⢠LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
⢠Maximum output frequency: 250MHz
⢠Output skew: 150ps (maximum)
⢠Part to part skew: 750ps (maximum)
⢠Additive phase jitter, RMS: < 0.03ps (typical)
⢠Full 3.3V and 2.5V or mixed 3.3V core, 2.5V output
supply modes
⢠0°C to 70°C ambient operating temperature
⢠Lead-Free package available
⢠Pin compatible with the MPC940L
BLOCK DIAGRAM
CLK_SEL
PCLK
nPCLK
0
LVCMOS_CLK
1
83940DY
PIN ASSIGNMENT
18
Q0:Q17
GND
GND
LVCMOS_CLK
CLK_SEL
PCLK
nPCLK
VDD
VDDO
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4 ICS83940D 21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
Q6
Q7
Q8
VDD
Q9
Q10
Q11
GND
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Pacakge
Top View
www.icst.com/products/hiperclocks.html
1
REV. B JUNE 15, 2004
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