ICS8312 Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
TABLE 5A. AC CHARACTERISTICS, V_DD = V_DDO = 3.3V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
f_MAX
tp_LH
tsk(o)
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 250MHz
tsk(pp) Part-to-Part Skew; NOTE 3, 5
t_R/ t_F
Output Rise Time; NOTE 4
odc
Output Duty Cycle
20% to 80%
f ≤ 200MHz
All parameters measured at f_MAX unless noted otherwise.
See Table 5C listed below for Notes 1 through 5.
Minimum
1.2
200
45
Typical
1.9
Maximum Units
250
MHz
2.5
ns
125
ps
800
ps
700
ps
55
%
TABLE 5B. AC CHARACTERISTICS, V_DD = V_DDO = 2.5V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
f_MAX
tp_LH
tsk(o)
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 250MHz
tsk(pp) Part-to-Part Skew; NOTE 3, 5
t_R/ t_F
Output Rise Time; NOTE 4
odc
Output Duty Cycle
20% to 80%
f ≤ 150MHz
All parameters measured at fMAX unless noted otherwise.
See Table 5C listed below for Notes 1 through
Minimum
1.4
200
45
Typical
2.3
Maximum Units
250
MHz
3.2
ns
150
ps
1.1
ns
700
ps
55
%
TABLE 5C. AC CHARACTERISTICS, V_DD = V_DDO = 1.8V±0.2V, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
tp_LH
tsk(o)
Output Frequency
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 200MHz
200
MHz
1.6
3.3
4.8
ns
140
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
2.3
ns
t /t
Output Rise Time; NOTE 4
RF
odc
Output Duty Cycle
20% to 80%
200
f ≤ 100MHz
45
800
ps
55
%
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from V_DD/2 of the input to V_DDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDO/2.
NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at V_DDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8312AY
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5
REV. C JUNE 14, 2004