ICS8312 Datasheet, PDF (2/12 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8312
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 5, 8, 12,
16, 17, 21,
25, 29
GND
Power
Power supply ground.
2, 7
V_DD
Power
Core supply pins.
3
CLK_EN
Input
Pullup
Synchronous control for enabling and disabling clock outputs.
LVCMOS / LVTTL interface levels.
4
CLK
Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
6
OE
Input
Pullup
Output enable. Controls enabling and disabling of outputs
Q0 thru Q11. LVCMOS / LVTTL interface levels.
9, 11, 13, 15,
18, 20, 22,
24, 26, 28,
30, 32
Q11, Q10, Q9, Q8,
Q7, Q6, Q5,
Q4, Q3, Q2,
Q1, Q0
Output
Q0 thru Q11 outputs. LVCMOS / LVTTL interface levels.
10, 14, 19,
23, 27, 31
V_DDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
Parameter
Input Capacitance
C_PD
Power Dissipation Capacitance
(per output)
R_PULLUP
R_PULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
R
OUT
Output Impedance
Test Conditions
V_DDO = 3.465V
V_DDO = 2.625V
V_DDO = 2V
V_DDO = 3.3V ± 5%
V = 2.5V ± 5%
DDO
V_DDO = 1.8V ± 0.2V
Minimum
Typical
4
51
51
7
7
10
Maximum
19
18
16
Units
pF
pF
pF
pF
KΩ
KΩ
Ω
Ω
Ω
TABLE 3A. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Control Inputs
OE
CLK_EN
0
X
1
0
1
1
Output
Q0:Q11
Hi-Z
LOW
Follows CLK input
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
OE
CLK_EN
CLK
1
1
0
1
1
1
Outputs
Q0:Q11
LOW
HIGH
8312AY
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2
REV. C JUNE 14, 2004