ICS83052I Datasheet, PDF (5/12 Pages) Integrated Circuit Systems – 2:1, SINGLE-ENDED MULTIPLEXER

Integrated
Circuit
Systems, Inc.
ICS83052I
2:1, SINGLE-ENDED MULTIPLEXER
TABLE 5D. AC CHARACTERISTICS, V_DD = V_DDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum
f_MAX
Output Frequency
tp_LH
Propagation Delay, Low to High;
NOTE 1
tp_HL
Propagation Delay, High to Low;
NOTE 1
250
2.2
2.7
3.2
2.2
2.7
3.2
tsk(i)
Input Skew; NOTE 4
28
123
tsk(pp)
Part-to-Part Skew; NOTE 2, 4
400
Buffer Additive Phase Jitter, RMS;
155.52MHz,
tjit
refer to Additive Phase Jitter section,
Integration Range:
0.22
NOTE 3
12kHz - 20MHz
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
300
700
45
55
MUX_ISOLATION MUX Isolation
45
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: Driving only one input clock.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ns
ps
ps
ps
ps
%
dB
TABLE 5E. AC CHARACTERISTICS, V_DD = 2.5V ± 5%, V_DDO = 1.8V ± 5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
tp_LH
tp_HL
tsk(i)
Output Frequency
Propagation Delay, Low to High;
NOTE 1
Propagation Delay, High to Low;
NOTE 1
Input Skew; NOTE 4
250
MHz
2.1
3.1
4.1
ns
2.1
3.1
4.2
ns
19
73
ps
tsk(pp)
tjit
t_R / t_F
odc
Part-to-Part Skew; NOTE 2, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 3
Output Rise/Fall Time
Output Duty Cycle
155.52MHz,
Integration Range:
12kHz - 20MHz
20% to 80%
350
ps
0.19
ps
350
850
ps
45
55
%
MUX_ISOLATION MUX Isolation
45
dB
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 3: Driving only one input clock.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83052AGI
www.icst.com/products/hiperclocks.html
6
REV. A AUGUST 2, 2005