ICS552-02 Datasheet, PDF (5/6 Pages) Integrated Circuit Systems – LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER

PRELIMINARY INFORMATION
ICS552-02
LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK
AC Electrical Characteristics
VDD = 2.5V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Propagation Delay
t_OR 0.8 to 2.0 V, C_L=15 pF
1.5
t_OF 2.0 to 0.8 V, C_L=15 pF
1.5
Note 1
3.5
Output to output skew
Note 2 Rising edges at VDD/2
0
Input A to Input B skew
Note 3
0
Max.
200
50
50
Units
MHz
ns
ns
ns
ps
ps
VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Propagation Delay
t_OR 0.8 to 2.0 V, C_L=15 pF
1.0
t_OF 2.0 to 0.8 V, C_L=15 pF
1.0
Note 1
3.0
Output to output skew
Note 2 Rising edges at VDD/2
0
Input A to Input B skew
Note 3
0
Max.
200
50
50
Units
MHz
ns
ns
ns
ps
ps
VDD = 5.0V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise
Parameter
Symbol
Conditions
Min. Typ.
Input Frequency
0
Output Rise Time
Output Fall Time
Propagation Delay
t_OR 0.8 to 2.0 V, C_L=15 pF
0.7
t_OF 2.0 to 0.8 V, C_L=15 pF
0.7
Note 1
2.8
Output to output skew
Note 2 Rising edges at VDD/2
0
Input A to Input B skew
Note 3
0
Max.
200
50
50
Units
MHz
ns
ns
ns
ps
ps
Notes: 1. With rail-to-rail input clock.
2. Between any two outputs with equal loading.
3. Propagation delay matching through the part.
4. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock
generators.
MDS 552-02 B
5
Revision 050401
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