ICS552-02 Datasheet, PDF (2/6 Pages) Integrated Circuit Systems – LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER

PRELIMINARY INFORMATION
ICS552-02
LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK
Pin Assignment
Input Source Select
OE 1
VDD 2
Q0 3
Q1 4
Q2 5
Q3 6
GND 7
INB 8
16 SELA
15 VDD
14 Q7
13 Q6
12 Q5
11 Q4
10 GND
9 INA
SELA
0
1
Input
INB
INA
16 Pin TSSOP
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin
Name
OE
VDD
Q0
Q1
Q2
Q3
GND
INB
INA
GND
Q4
Q5
Q6
Q7
VDD
SELA
Pin
Type
Input
Power
Output
Output
Output
Output
Power
Input
Input
Power
Output
Output
Output
Output
Power
Input
Pin Description
Output Enable. Tri-states outputs when low. Internal pull-up resistor.
Connect to +2.5V, +3.3V or +5.0V. Must be the same as pin 15.
Clock Output 0
Clock Output 1
Clock Output 2
Clock Output 3
Connect to ground.
Clock Input B. 5V tolerant input.
Clock Input A. 5V tolerant input.
Connect to ground.
Clock Output 4
Clock Output 5
Clock Output 6
Clock Output 7
Connect to + 2.5V, +3.3V or +5.0V. Must be the same as pin 2.
Selects either INA or INB. Internal pull-up resistor.
External Components
A minimum number of external components are required for proper operation. Decoupling capacitors of
0.01 µF should be connected between VDD on pin 2 and GND on pin 7, and between VDD on pin 15 and
GND on pin 10, as close to the device as possible. A 33 Ω series terminating resistor should be used on
each clock output if the trace is longer than 1 inch.
To achieve the low output skews that the ICS552-02 is capable of, careful attention must be paid to board
layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace
geometries. If they do not, the output skew will be degraded. For example, using a 30 Ω series termination
on one output (with 33Ω on the others) will cause at least 15ps of skew.
MDS 552-02 B
2
Revision 050401
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