ICS2059-02 Datasheet, PDF (5/11 Pages) Integrated Circuit Systems – Clock Multiplier and Jitter Attenuator

ICS2059-02
Clock Multiplier and Jitter Attenuator
A “normalized” PLL loop bandwidth may be calculated
as follows:
NBW = ^R------^S----^×----^I---^C---^P-----^×---³-⁵---⁴-⁷--⁵--⁵--
N
The “normalized” bandwidth equation above does not
take into account the effects of damping factor or the
second pole. However, it does provide a useful
approximation of filter performance.
The loop damping factor is calculated as follows:
Damping Factor = R_S ×
-3-6--7-2--5--5-----^×----I--^C-----^P-----^×-----C----^S--
N
Where:
R_S = Value of resistor in loop filter (Ohms)
I_CP = Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
C_S = Value of capacitor C₁ in loop filter (Farads)
As a general rule, the following relationship should be
maintained between components C₁ and C₂ in the loop
filter:
C_P
=
C_----S-
20
Charge Pump Current Table
R_SET
1.4 MΩ
680 kΩ
540 kΩ
120 kΩ
Charge Pump Current
(I_CP)
10 µA
20 µA
25 µA
100 µA
Special considerations must be made in choosing loop
components C_S and C_P. These recommendations can
be found in the design aid tools section of
www.icst.com.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω. (The optional series termination resistor
is not shown in the External Component Schematic.)
Decoupling Capacitors
As with any high-performance mixed-signal IC, the
ICS2059-02 must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the ICS2059-02 should use one common connection to
the PCB power plane as shown in the diagram on the
next page. The ferrite bead and bulk capacitor help
reduce lower frequency noise in the supply that can
lead to output clock phase modulation.
Recommended Power Supply Connection
for Optimal Device Performance
Connection to 3.3V
Power Plane
Ferrite
Bead
VDD Pin
VDD Pin
Bulk Decoupling Capacitor
(such as 1 F Tantalum)
VDD Pin
0.01 F Decoupling Capacitors
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground, shown as C_L in the External Component
Schematic. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device.
MDS 2059-02 C
5
Revision 031605
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel [phone] ● www.icst.com