ICS2059-02 Datasheet, PDF (4/11 Pages) Integrated Circuit Systems – Clock Multiplier and Jitter Attenuator

ICS2059-02
Clock Multiplier and Jitter Attenuator
Referencing the External Component Schematic on
this page, the external loop filter is made up of the
components R_Z, C₁ and C₂. R_SET establishes PLL
charge pump current and therefore influences loop
filter characteristics.
Design aid tools for configuring the loop filter can be
found at www.icst.com, including on-line and PC-based
calculators.
External Component Schematic
C_L
C_L
(Refer to Crystal
Tuning section)
Crystal
X1
1
X2
16
VDD
2
15 ISEL
VDD
3
14 ICLK1
VDD
4
VIN
5
13 ICLK2
12 SEL0
P
R_S
GND
GND
6
7
11 CLK
10 ^SEL1
C_{S CHGP}
8
9
ISET
16-pin (173 mil) TSSOP
R _SET
Recommended Loop Filter Values Vs. Output Frequency Range Selection
Crystal
SEL1 SEL0 _Multiplier
(N)
00
2592
01
2430
10
1728
11
1716
M0
128
M1
1
R_SET
180 kΩ
120 kΩ
330 kΩ
330 kΩ
120 kΩ
1 MΩ
R_S
C_S
820 kΩ
560 kΩ
680 kΩ
680 kΩ
330 kΩ
22 kΩ
0.47 µF
0.68 µF
0.68 µF
0.68 µF
1 µF
1 µF
C_P
1.8 nF
3.3 nF
3.9 nF
3.9 nF
3.3 nF
3.3 nF
Loop
Bandwidth
(-3dB point)
11.2 Hz
11.8 Hz
11.5 Hz
11.5 Hz
14.5 Hz
204.2 Hz
Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating
Damping
Factor
3.00
2.97
3.17
3.18
3.16
3.08
MDS 2059-02 C
4
Revision 031605
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