ICS93776 Datasheet, PDF (4/8 Pages) Integrated Circuit Systems – Low Cost DDR Phase Lock Loop Zero Delay Buffer

ICS9377 6
Timing Requirements
T_A = 0 - 70°C; Supply Voltage AV_DD, V_DD = 2.50V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Operating Clock Frequency¹
freq_op Input Voltage level: 0-2.50V
Input Clock Duty Cycle¹
Clock Stabilization¹
d_tin
t_STAB
from VDD = 2.5V to 1% target frequency
1. Guaranteed by design, not 100% tested in production.
MIN TYP MAX UNITS
22
340 MHz
40 50 60
%
100
µs
Switching Characteristics
T_A = 0 - 70°C; Supply Voltage AV_DD, V_DD = 2.50V ± 0.20V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Cycle to cycle Jitter^1,2
t_c-c
66 MHz to 266 MHz
100
ps
Phase Error¹
Output to output Skew¹
Duty Cycle (Sign Ended)^1,3
Rise Time, Fall Time⁴
Output Differential Pair
Crossing Voltage
t_pe
T_skew
DC
t_R , t_f
V_OC
66 MHz to 267 MHz
Load=120Ω/14pF
V_DD=2.50V
-150
48
1.23
150
ps
100
ps
52
%
950
ps
1.32
V
1. Guaranteed by design, not 100% tested in production.
2. Refers to transistion on non-inverting period.
3. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies.
This is due to the formular: duty_cycle=t_wH/t_C, where the cycle time (t_C)decreases as the frequency increases.
0793A—03/08/05
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