ICS93776 Datasheet, PDF (2/8 Pages) Integrated Circuit Systems – Low Cost DDR Phase Lock Loop Zero Delay Buffer

ICS9377 6
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PIN NAME
DDRC0
DDRT0
VDD
DDRT1
DDRC1
GND
SCLK
CLK_INT
CLK_INC
VDDA
GND
VDD
DDRT2
DDRC2
GND
DDRC3
DDRT3
18
FB_OUTC
19
FB_OUTT
20
FB_INT
21
FB_INC
22
SDATA
23
VDD
24
DDRT4
25
DDRC4
26
DDRT5
27
DDRC5
28
GND
PIN TYPE DESCRIPTION
OUT
OUT
PWR
OUT
OUT
PWR
IN
IN
IN
PWR
PWR
PWR
OUT
OUT
PWR
OUT
OUT
OUT
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
"True" reference clock input.
"Complementary" reference clock input.
2.5V power for the PLL core.
Ground pin.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
Complement single-ended feedback output, dedicated
external feedback. It switches at the same frequency
as other DDR outputs, This output must be connect to
FB_INC.
OUT
True single-ended feedback output, dedicated external
feedback. It switches at the same frequency as other
DDR outputs, This output must be connect to FB_INT.
IN
IN
I/O
PWR
OUT
OUT
OUT
OUT
PWR
True single-ended feedback input, provides feedback
signal to internal PLL for synchronization with
CLK_INT to eliminate phase error.
Complement single-ended feedback input, provides
feedback signal to internal PLL for synchronization
with CLK_INT to eliminate phase error.
Data pin for SMBus circuitry, 5V tolerant.
Power supply, nominal 2.5V
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complementary" Clock of differential pair output.
Ground pin.
0793A—03/08/05
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