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ICS9248-171 Datasheet, PDF (4/15 Pages) Integrated Circuit Systems – AMD - K7TM System Clock Chip
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ICS9248-171
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
Bit 2,
Bit 7:4
Bit 3
Bit 1
Bit 0
FS3 FS2 FS1 FS0 CPUCLK SDRAM PCICLK
Bit2 Bit7 Bit6 Bit5 Bit4 (MHz) (MHz) (MHz)
0 0000
66.66
66.66 33.33
0 0 0 0 1 66.66 100.00 33.33
0 0 0 1 0 100.00 66.66 33.33
0 0 0 1 1 100.00 100.00 33.33
0 0 1 0 0 100.00 133.33 33.33
0 0 1 0 1 120.00 120.00 30.00
0 0 1 1 0 133.33 100.00 33.33
0 0 1 1 1 133.33 133.33 33.33
0 1 0 0 0 90.00 90.00 30.00
0 1 0 0 1 101.00 101.00 33.67
0 1 0 1 0 100.00 66.66 33.33
0 1 0 1 1 100.00 100.00 33.33
0 1 1 0 0 100.00 133.33 33.33
0 0 1 0 1 126.00 126.00 31.50
0 1 1 1 0 133.33 100.00 33.33
0 1 1 1 1 133.33 133.33 33.33
1 0 0 0 0 102.00 102.00 34.00
1 0 0 0 1 102.00 136.00 34.00
1 0 0 1 0 136.00 102.00 34.00
1 0 0 1 1 136.00 136.00 34.00
1 0 1 0 0 103.00 103.00 34.33
1 0 1 0 1 103.00 137.33 34.33
1 0 1 1 0 137.33 103.00 34.33
1 0 1 1 1 137.33 137.33 34.33
1 1 0 0 0 105.00 105.00 35.00
1 1 0 0 1 105.00 140.00 35.00
1 1 0 1 0 140.00 140.00 35.00
1 1 0 1 1 107.00 107.00 35.66
1 1 1 0 0 107.00 142.66 35.66
1 1 1 0 1 142.66 142.66 35.66
1 1 1 1 0 110.00 110.00 36.66
1 1 1 1 1 146.66 146.66 36.66
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
AGP
(MHz)
66.66
66.66
66.66
66.66
66.66
60.00
66.66
66.66
60.00
67.33
66.66
66.66
66.66
63.00
66.66
66.66
67.99
67.99
67.99
67.99
68.66
68.66
68.66
68.66
69.99
69.99
69.99
71.33
71.33
71.33
73.33
73.33
Spread Precentage
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
PWD
00000
Note1
0
0
0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I2C readback of the power up default indicates the revision ID in bits 2, 7:4 as shown.
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