ICS9248-171 Datasheet, PDF (2/15 Pages) Integrated Circuit Systems – AMD - K7TM System Clock Chip

ICS9248-171
Advance Information
Pin Descriptions
PIN NUMBER PIN NAME
1
D G _S TO P #¹
2
PD#¹
4
5
3, 11, 16, 23, 29,
34, 41, 48
8, 17, 28, 35, 40
6
7
9
10
12
20, 19, 15, 14, 13
18
21
22
24
27
25, 26, 30, 31, 32,
33, 36, 37, 38, 39,
42, 43
44
X1
X2
GND
VDD
AVDD
FS0^{2, 3}
REF0
FS1^{2, 3}
AGP0
AGP1
PCICLK_F
FS2^{1, 3}
PCICLK
(5:4) (2:0)
PCICLK3
MODE^{1, 3}
AVDD48
FS3^{2, 3}
48MHz
SCLK
P CI_S TO P # ¹
SDRAM10
SDRAM
(12:11, 9:0 )
SDATA
45, 47
CPUCLKT (1:0)
46
CPUCLKC0
TYPE
IN
IN
IN
OUT
PWR
PWR
PWR
IN
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
IN
PWR
IN
OUT
IN
IN
OUT
OUT
I/O
OUT
OUT
DESCRIPTION
DG_STOP halts SDRAM and/or AGP clocks at logic "0" when driven low.
The stops selection can be programed through I²C.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Crystal input,nominally 14.318M Hz.
Crystal output, nominally 14.318MHz.
Ground pins
Power supply pins, nominal 3.3V
Analog power supply pin, nominal 3.3V
Frequency select pin.
14.318 M Hz reference clock.
Frequency select pin.
AGP outputs defined as 2X PCI. These may not be stopped.
AGP outputs defined as 2X PCI. These may not be stopped.
Free running PCICLK not stoped by PCI_STOP#
Frequency select pin.
PCI clock outputs.
PCI clock output.
Function select pin, 1=Desktop M ode, 0=M obile M ode.
Analog power supply pin, nominal 3.3V
Frequency select pin.
48MHz output clock
Clock input of I²C input, 5V tolerant input
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
SDRAM clock output.
SDRAM clock outputs.
Data pin for I²C circuitry 5V tolerant
"True" clocks of differential pair CPU outputs. These open drain outputs
need an external 1.5V pull-up.
"Complementory" clocks of differential pair CPU outputs. This open drain
output need an external 1.5V pull-up.
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Internal pull-down resistor of 120K to GND.
3: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
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