ICS9222-01 Datasheet, PDF (4/6 Pages) Integrated Circuit Systems – Dual Memory Clock Generator

ICS9222 - 01
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input / Supply / Outputs
T_A = 0 - 70C; Supply Voltage V_DD = 3.3 V +/-10% (unless otherwise stated)
PARAMETER
SYMBOL
Supply Voltage
REFCLK Input cycle time
Input Cycle-to-Cycle Jitter
Input Duty Cycle over 10K cycles
Input frequency of modulation
Modulation index
Phase detector input cycle time at PCLK (1:0) & SYNCLK (1:0)
Initial phase error at phase detector inputs
Phase detector input duty cycle over 10K cycles
Input rise & fall times (measured at 20%-80% of input voltage)
V_DD
t_CYCLE,IN
t_J,IN
DC_IN
F_M,IN
P_M,IN
t_CYCLE,PD
t_err,init
DC_IN,PD
for PCLK (1:0), SYNCLK (1:0) & REFCLK
t_IR, t_IF
Input capacitance at PCLK (1:0) & SYNCLK (1:0) & REFCLK
Input capacitance matching at PCLK (1:0) & SYNCLK (1:0)
Input capacitance at CMOS pins
Input (CMOS) signal low voltage
C_IN,PD
∆ C_IN,PD
C_IN,CMOS
V_IL
Input (CMOS) signal high voltage
REFCLK input low voltage
REFCLK input high voltage
Input signal low voltage for PD inputs and STOP_CLK
V_IH
V_IL,R
V_IH,R
V_IL,R
Input signal high voltage for PD inputs and STOP_CLK
V_IH,R
Input supply reference for REFCLK
Input supply reference for PD inputs
Phase detector phase error for distributed loop measured at
V_DD,IR
V_DD,IPD
PCLK (1:0) & SYNCLK (1:0)
Clock Cycle time
Cycle-to-cycle jitter at CLK (1:0) & CLKB (1:0)
t_ERR,PD
t_CYCLE
t_J
Total jitter over 2 ,3 or 4 cycles
Phase aligner phase step size CLK (1:0) & CLKB (1:0)
PLL output phase error when tracking SSC
Output crossing-point voltage
Output voltage during Clk Stop (CLK_STOP#=0)
t_J
t_STEP
t_ERR,SSC
V_X
V_X,STOP
Output Voltage swing
Output low voltage
Output high voltage
Output duty cycle over 10K cycles
V_COS
V_OL
V_OH
DC
Output cycle-to-cycle duty cycle error
Output rise & fall times (measured at 20%-80% of input voltage)
t_DC,ERR
for PCLK (1:0), SYNCLK (1:0) & REFCLK
Difference between rise and fall times on a single device (20%-80%)
Operating Supply Current 400MHz
t_CR,t_CF
t_CR,CF
MIN
3.135
10
-
40%
30
0.25
30
-0.5
25%
-
-
-
-
-
0.7
-
0.7
-
0.7
1.235
1.235
-100
2.5
-
-
1
-100
1.3
1.1
0.4
1
-
40%
-
300
-
MAX
3.465
40
250
60%
33
0.5
100
0.5
75%
1
7
0.5
10
0.3
-
0.3
-
0.3
-
3.465
3.465
100
3.75
60
100
-
100
1.8
2
1
-
2.35
60%
50
500
100
250
UNIT
V
ns
ps
t_CYCLE
kHz
%
ns
t_CYCLE,PD
t_CYCLE,PD
ns
pF
pF
pF
V_DD
V_DD
V_DD,IR
V_DD,IR
V_DD,IPD
V_DD,IPD
V
V
ps
ns
ps
ps
ps
ps
V
V
V
V
V
t_CYCLE
ps
ps
ps
mA
0274C—11/14/05
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