ICS9222-01 Datasheet, PDF (2/6 Pages) Integrated Circuit Systems – Dual Memory Clock Generator

ICS9222 - 01
Pin Descriptions
Pin #
1, 7, 21, 22
2
3, 11
6, 8, 18, 25
Name
VDD
REFCLK
VDDC
GND
4, 5, 9, 10 PCLK, SYNCLK
12
VDDIPD
13
CLK_ STOP#
14
PD#
15, 16, 17
19, 24
20, 23
26, 27, 28
MULT (2:0)
CLKB (1:0)
CLK (1:0)
FS (2:0)
Type
PWR
IN
PWR
PWR
IN
PWR
IN
IN
IN
OUT
OUT
IN
Description
3.3 V power supply
Reference clock
Power for phase aligners
Ground
Phase controller input, used to drive a phase aligner
that adjusts the phase of the busclk.
Voltage for phase detector inputs
Active low output enable/disable for CLK/CLKB
3.3V CMOS active low power down, the device is
powered down when the "(PD#) =0"
3.3V CMOS PLL Multiplier select, logic for selecting the
multiply ratio for the PLL from the input REFCLK
Clock output Complement
Clock output
3.3V CMOS Mode control, used in selecting bypass,
test, normal, and output test (OE)
0274C—11/14/05
2