ICS9222-01 Datasheet, PDF (1/6 Pages) Integrated Circuit Systems – Dual Memory Clock Generator

Integrated
Circuit
Systems, Inc.
ICS9222 - 01
Dual Memory Clock Generator
General Description
Features
The ICS9222-01 is a High-speed clock generator providing ^{• Compatible with all Direct Rambus™ based ICs}
two channels up to 450 MHz differential clock source for _{• Up to 450 MHz differential clock source for direct}
direct Rambus_memory system. It includes two independent
Rambus™ memory system
DDLL’s (Distributed Delay locked loop) and phase detection
mechanisms to synchronize eachdirect Rambus_ channel
•
Cycle to cycle jitter is less than 100 ps
clock to an external system clock. ICS9222-01 provides a • 3.3 ± 5% supply
solution for a broad range of Direct Rambus memory
applications. The device works in conjunction with the
ICS964S101, as well as 9250-22 and others (depending on
chipset).
•
Synchronization flexibility: Supports systems that need
clock domains of Rambus channel to synchronize with
system or processor clock, or systems that do not
require synchronization of the Rambus clock to another
system clock.
The ICS9222-01 power management support system turns • Excellent power management support
“off” the Rambus channel clock to minimize power
consumption for mobile and other power sensitive
applications. In “clock off” mode the device remains “on”
• REFCLK input is from the main clock generator such as
a 9250-22.
while the output is disabled, allowing fast transitions between
clock-off and clock–on states. In “power down” mode it
completely powers down for minimum power dissipation.
Block Diagram
CLK_STOP#
PD#
FS (2:0)
PCLK1
SYNCLK1
REFCLK
MULT (2:0)
2
PCLK0
SYNCLK0
Test MUX
Bypass MUX _Bypclk
GND
PLLclk
B
PLL
A
Phase
Detector
Phase
Aligner
Phase
Aligner
Phase
Detector
GND
GND
PAclk
Pin Configuration
VDDREF
1
28
REFCLK
2
27
VDDC
3
26
SYNCLK0
4
25
PCLK0
5
24
GND
6
23
VDDP
7
22
CLK1
GND
8
21
CLKB1
SYNCLK1
9
20
PCLK1 10
19
CLK0
VDDC 11
18
CLKB0
VDDIPD 12
17
CLK_STOP# 13
16
PD# 14
15
28-Pin TSSOP
FS0
FS1
FS2
GND
CLKB0
CLK0
VDDCLK
VDDCLK
CLK1
CLKB1
GND
MULT_0
MULT_1
MULT_2
0274C—11/14/05