ICS9212-13 Datasheet, PDF (4/7 Pages) Integrated Circuit Systems – Direct Rambus™ Clock Generator

ICS9212 - 13
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics-input/supply/Outputs
Parameters
Supply Voltage
Refclk Input cycle time
Input cycle-to-cycle Jitter
Input Duty cycle over 10k cycles
Input frequency of modulation
Modulation index
Phase detector input cycle time at PDclk/M & Synclk/N
Initial phase error at phase detector inputs
Phase detector input duty cycle over 10k cycles
Input rise & fall times ( measured at 20%-80% of input voltage) for
PDCLK/M & SYNCLK/N,&REfCLK
Input capacitance at PDCLK/M,Synclk/N,&REFCLK
Input Capacitance matching at PCLK/M & SYNCLK/N
Input capacitance at CMOS pins
Input (CMOS) signal low voltage
Input (CMOS) signal high voltage
REFCLK input low voltage
REFCLK input high voltage
Input signal low voltage for PD inputs and STOP
Input signal high voltage for PD inputs and STOP
Input supply referance for REFCLK
Input supply referance vfor PD inputs
Phase detector phase error for distributed loop measured at
PDCLK/M & SYNCLK/N(rising
Cycle cycle time
Cycle-to-cycle jitter at Busclk/BUSCLKB (533 MHz)
Total jitter over 1 - 6 cycles (533MHz)
Phase aligner, phase step size (BSCLK/BUSCLKB)
PLL out put phase error when tracking SSC
Symbol
VDD
t_CYCLE,IN
t_J,IN
DC_IN
F_m,in
P_M,IN
t_CYCLE,PD
T_err,init
D_CIN,PD
T_IR,T_IF
C_IN,PD
DC_IN,PD
C_IN,CMOS
V_IL
V_IH
V_IL,R
V_IH,R
V_IL,PD
V_IH,PD
V_DD,IR
V_DDI,PD
t_ERR,PD
t_CYCLE
t_J
t_J
t_STEP
t_ERR,SSC
Min
3.135
10
-
40%
30
0.25
30
-0.5
25%
-
-
-
-
-
0.7
-
0.7
-
0.7
1.3
1.3
-100
2.5
-
-
1
-100
Max
3.465
40
250
60%
33
0.5
100
0.5
75%
1
7
0.5
10
0.3
-
0.3
-
0.3
-
3.465
3.465
100
3.75
40
30
-
100
Unit
V
ns
ps
t_CYCLE
kHz
%
ns
t_CYCLE,PD
t_CYCLE,PD
ns
pF
pF
pF
Vdd
Vdd
Vddi,R
Vddi,R
Vddi,PD
Vddi,PD
V
V
ps
ns
ps
ps
ps
ps
Out put crossing-point voltage
Output voltage swing
Output high voltage
Out put duty cycle over 10k cycle
Output cycle -to-cycle duty cycle error
Output rise & fall times ( measured at 20%-80% of output voltage)
Difference between rise and fall times on a single device(20%-80%)
Opearting Supply Current
V_X
V_COS
V_H
DC
t_DC,ERR
t_CR,t_CF
t_CR,CF
I_DD
1.3
0.4
-
40%
-
300
-
1.8
0.6
2
60%
50
500
100
150
V
V
V
t_CYCLE
ps
ps
ps
mA
0272F—08/08/07
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