ICS9212-13 Datasheet, PDF (3/7 Pages) Integrated Circuit Systems – Direct Rambus™ Clock Generator

ICS9212 - 13
PLL Divider Selection and PLL Values (PLLCLK = REFCLK*A/B)
Multo Mult1
A
B
PLLCLK for REFCLK=50MHz PLLCLK for REFCLK=66.66MHz
0
0
4
1
Reserved
266.6
0
1
6
1
300
400.0
1
0
16
3
266.7
355.5
1
1
8
1
400
533.3
Bypass and Test Mode Selection
Mode
FS0
FS1
Normal
0
0
Bypass
1
0
Test
1
1
Vendor Test A
0
0
Vendor Test B
1
0
Reserved
1
1
Output Test (OE)
0
1
FS2 Bypclk (int.) BusClk BusClkB
0
Gnd
PAclk
PAclkB
0
PLLclk
PLLclk
PLLclkB
0
Refclk
Refclk
RefclkB
1
-
-
-
1
-
-
-
1
-
-
-
X
-
Hi-Z
Hi-Z
Power Management Modes
State
PwrDnB
NORMAL
1
Clk Off
1
Powerdown
0
StopB
1
0
X
0272F—08/08/07
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