ICS9212-13 Datasheet, PDF (2/7 Pages) Integrated Circuit Systems – Direct Rambus™ Clock Generator

ICS9212 - 13
Pin Descriptions
Pin #
1
2
3
4
5
6,7
8
9
10
11
12
Name
VDDREF
REFCLK
VDD1
GND1
GND3
PCLK/M, SYNCLK/N
GND2
VDD2
VDDPD
BUSCLK_ STOP#
PD#
14,15
16
17
18
19
20
21
22
13,23,24
MULTI (0:1)
VDD_OUT
GND_OUT
BUSCLKC
N/C
BUSCLKT
GND_OUT
VDD_OUT
FS(0:2)
Type
REFV
IN
PWR
PWR
PWR
IN
PWR
PWR
REFV
IN
IN
IN
PWR
PWR
OUT
N/C
OUT
PWR
PWR
IN
Description
Reference voltage for refclk, to be connected to CK133
Reference clock, to be connected to CK133
3.3 V power supply used for PLL
Ground for PLL
Ground for control inputs
Phase controller input, used to drive a phase aligner
that adjusts the phase of the busclk.
Ground for phase aligner
3.3 V power supply used for phase aligner
Reference voltage for phase detector inputs connected
to the controller
Active low output enable/disable
3.3V CMOS active low power down, the device is
powered down when the "(PD#) =0"
3.3V CMOS PLL Multiplier select, logic for selecting
the multiply ratio for the PLL from the input REFCLK
3.3V supply for clock out puts
Ground for clock outputs
Out put clock connected to the Rambus channel. This
output is the complement of BUSCLK
NOT USED
Output clock connected to the Rambus channel. This
output is the true component of BUSCLK
Ground for clock outputs
3.3V supply for clock out puts
3.3V CMOS Mode control, used in selecting bypass,
test, normal, and output test (OE)
0272F—08/08/07
2