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| ICS83947I-147 Datasheet, PDF (4/10 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER | |||
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Integrated
Circuit
Systems, Inc.
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tPD
tsk(o)
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 5
tsk(pp)
tjit(Ã)
Part-to-Part Skew; NOTE 3, 5
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
f ⤠250MHZ
Measured on
rising edge @VDDO/2
Measured on
rising edge @VDDO/2
(12KHz to 20MHz)
250
MHz
2
4.2
ns
115
ps
500
ps
0.2
ps
tR / tF
tPW
odc
Output Rise/Fall Time
Output Pulse Width
Output Duty Cycle
0.8V to 2.0V
f > 133MHz
f ⤠133MHz
0.2
tPeriod/2 - 1
40
1
ns
tPeriod/2 + 1
ns
60
%
tEN
Output Enable Time; NOTE 4
10
ns
tDIS
Output Disable Time; NOTE 4
10
ns
tS
Clock Enable Setup Time
0
ns
tS
Clock Enable Hold Time
1
ns
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V ± 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tPD
tsk(o)
Output Frequency
Propagation Delay, NOTE 1
Output Skew; NOTE 2, 5
tsk(pp)
tjit(Ã)
Part-to-Part Skew; NOTE 3, 5
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
f ⤠250MHZ
Measured on
rising edge @VDDO/2
Measured on
rising edge @VDDO/2
(12KHz to 20MHz)
250
MHz
2.4
4.5
ns
130
ps
600
ps
0.1
ps
tR / tF
Output Rise/Fall Time
20% - 80%
300
800
ps
tPW
Output Pulse Width
tPeriod/2 - 1.2
tPeriod/2 + 1.2
ns
tEN
Output Enable Time; NOTE 4
10
ns
tDIS
Output Disable Time; NOTE 4
10
ns
tS
Clock Enable Setup Time
0
ns
tS
Clock Enable Hold Time
1
ns
All parameters measured at frequencies less than or equal to 250MHz unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
4
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