ICS83947I-147 Datasheet, PDF (3/10 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-9 LVCMOS/LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V_DD
Inputs, V_I
Outputs, V_O
Package Thermal Impedance, θ_JA
Storage Temperature, T_STG
4.6V
-0.5V to V_DD + 0.5 V
-0.5V to V_DDO + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
ICS83947I-147
LOW SKEW, 1-TO-9
LVCMOS/LVTTL FANOUT BUFFER
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V_DD = V_DDO = 3.3V±0.3V OR 2.5V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
V_DD
Core Supply Voltage
3.0
3.3
3.6
2.375
2.5
2.625
V_DDO
Output Supply Voltage
3.0
3.3
3.6
2.375
2.5
2.625
I_DD
Input Supply Current
50
I
Output Supply Current
9
DDO
Units
V
V
V
V
mA
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, V_DD = V_DDO = 3.3V±0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V_IH
Input High Voltage
V_IL
Input Low Voltage
I_IN
Input Current
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
2
-100
3.6
V
0.8
V
µA
V_OH
Output High Voltage; NOTE 1
I_OH = -20mA
2.5
V
V_OL
Output Low Voltage; NOTE 1
I_OL = 20mA
0.4
V
NOTE 1: Outputs terminated with 50Ω to V_DDO/2. See Parameter Measurement Information Section, 3.3V Output Load Test
Circuit Diagram.
TABLE
4B.
LVCMOS/LVTTL
DC
CHARACTERISTICS,
V
DD
=
V
DDO
=
2.5V±5%,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions Minimum Typical Maximum Units
V_IH
Input High Voltage
CLK0, CLK1
V_IL
Input Low Voltage
CLK_SEL, CLK_EN, OE
2
V_DD + 0.3
V
-0.3
1.3
V
-0.3
0.8
V
I_IH
Input High Current
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
V_DD = V_IN = 2.625V
5
µA
I_IL
Input Low Current
CLK0, CLK1, OE,
CLK_SEL, CLK_EN
V_DD = 32.625V,
V_IN = 0V
-150
µA
V_OH
Output High Voltage; NOTE 1
1.8
V
V_OL
Output Low Voltage; NOTE 1
0.5
V
NOTE
1:
Outputs
terminated
with
50Ω
to
V /2.
DDO
See
Parameter
Measurement
Information
Section,
2.5V
Output
Load
Test
Circuit Diagram.
83947AYI-147
http://www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 24, 2004
3