ICS8343-01 Datasheet, PDF (4/10 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER

Integrated
Circuit
Systems, Inc.
ICS8343-01
LOW SKEW, 1-TO-16
LVCMOS / LVTTL FANOUT BUFFER
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, V_DD = V_DD1 = V_DD2 = 3.3V±5% OR 2.5V±5%;
V
DD
=
3.3V±5%,
V
DD1
=
V
DD2
=
2.5V±5%,
TA
=
0°
TO
70°C
Symbol Parameter
Test Conditions
Minimum Typical
OE1, OE2
2
V_IH
Input High Voltage
CLK
2
OE1, OE2
-0.3
V
Input Low Voltage
IL
CLK
-0.3
I_IH
OE1, OE2
Input High Current
CLK
V_DD = V_IN = 3.465V or 2.625V
V_DD = V_IN = 3.465V or 2.625V
I_IL
Input Low Current
OE1, OE2
CLK
V_DD = 3.465V or 2.625V,
V_IN = 0V
V_DD = 3.465V or 2.625V,
V_IN = 0V
-150
-5
V_OH
Output High Voltage; NOTE 1
V_DD1 = V_DD2 = 3.465V
V_DD1 = V_DD2 = 2.625V
2.6
1.8
V_OL
Output Low Voltage; NOTE 1
V_DD1 = V_DD2 = 3.465V or 2.625V
I_OZL
Output Tristate Current Low
I_OZH
Output Tristate Current High
NOTE 1: Outputs terminated with 50Ω to V_DDx/2. See Parameter Measurement Information,
"Output Load Test Circuit Diagrams".
Maximum
V_DD + 0.3
V_DD + 0.3
0.8
1.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
0.5
V
5
µA
5
µA
TABLE
5A.
AC
CHARACTERISTICS,
V
DD
=
V
DD1
=
V
DD2
=
3.3V±5%,
TA
=
0°
TO
70°C
Symbol
f_MAX
t_pLH
tsk(o)
tsk(pp)
t_R / t_F
odc
Parameter
Output Frequency
Propagation Delay;
NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew;
NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
Test Conditions
IJ 200MHz
Measured on rising edge @V_DDx/2
Measured on rising edge @V_DDx/2
20% to 80%
IJ 133MHz
Minimum
2.0
0.4
45
Typical
Maximum
200
4.0
250
700
1.5
55
Units
MHz
ns
ps
ps
ns
%
t_PW
Output Pulse Width
ƒ> 133MHz
t_PERIOD/2 - 0.25 t_PERIOD/2 t_PERIOD/2 + 0.25 ns
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Measured from V_DD/2 of the input to V_DDx/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V_DDx/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at V_DDx/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8343AY-01
www.icst.com/products/hiperclocks.html
4
REV. B SEPTEMBER 16, 2004